1. Field of the Invention
The invention relates in general to a clock synchronizing circuit, and more particularly to a clock synchronizing circuit applied in a synchronous mirror delay (SMD) block.
2. Description of the Related Art
Wide-bandwidth memory systems require increasingly higher capacity and speed in operation. Conventionally, the external clock inputted to the memory system will be registered in an input buffer and processed in a clock driver to generate an internal clock, and the internal clock is a delayed signal of the external clock. In order to improve the memory performance, a clock synchronizing circuit is used to remove the clock skew between the external clock and internal clock.
Conventional phased-locked loop (PLL) and delay-locked loop (DLL) circuits do a good job of suppressing the clock skew. However, they are feedback circuits and require 50 clock cycles or more to achieve locking of the external clock and internal clock, resulting in a large standby current.
Comparatively, the SMD has the fast locking characteristic in recovering from power-down or standby mode within two cycles of the system clock. In other words, the power supply can be turned off completely in standby mode, and the recovery from standby mode can be obtained within a few clocks after power setting time.
FIG. 1A and FIG. 2 are respectively a block diagram of a conventional SMD block and a timing diagram of the relevant clocks in operation of the SMD block in FIG. 1A. As shown in FIG. 1A and FIG. 2, a SMD block 100 includes a delay monitor circuit (DMC) 102, forward delay array (FDA) 104, mirror control circuit (MCC) 106 and backward delay array (BDA) 108. Each of the FDA 104, MCC 106 and BDA 108 includes a number of stages of delay units (not shown in the figure). An external clock ECLK is first inputted to an input buffer 110, and delayed by a time d1 to output a clock A. The DMC 102 of the SMD block 100 then receives the clock A and delays the clock A by a time (d1+d2) to generate a clock B. Following that, the FDA 104 receives the clock B and delays the clock B to generate a clock Cn at the n-th stage of delay unit.
Next, the MCC 106 triggers out a clock Dn with a negative pulse at the n-th stage of delay unit according to the clocks A and Cn, and the clock Dn is delayed by a time tv relative to the clock B. Afterward, the BDA 108 receives the clock Dn, delays the clock Dn by the time tv to generate a clock E and converts the clock E to a clock F with a positive pulse. Finally, the clock F is outputted to a clock driver 120 and delayed by a time d2 through the clock driver 120 to generate an internal clock ICLK.
Totally, the internal clock ICLK will be delayed by a time (d1+(d1+d2)+tv+tv+d2)=2(d1+d2+tv) relative to the external clock ECLK. If the time tv is equal to (Tk−d1−d2), wherein Tk is a clock period of the external clock ECLK, the delay time of the internal clock ICLK will be twice the clock period Tk. Consequently, as shown in FIG. 2, the internal clock ICLK will synchronize the external clock ECLK during the third clock of the external clock ECLK. However, the above-mentioned SMD block 100 has the following issues.
(1) As shown in FIG. 1B, it is an example of the prior art SMD circuit in FIG. 1A. Since the signal Dn is the NAND2 result of the signals A and Cn, this will result in the condition as FIG. 3, the duty cycle td2 of the internal clock ICLK may not be the same as the duty cycle td1 of the external clock ECLK even the rising edge of the internal clock ICLK can synchronize the rising edge of the external clock ECLK. This will lead to an error operation in a double data rate (DDR) application since DDR will output data during both rising edge and falling edge.
(2) As shown in FIG. 4, the second rising edge of the clock A is supposed to generate a negative pulse Dn_1 of the clock Dn and start to propagate the negative pulse Dn_1 through the BDA 108. However, an unnecessary negative pulse Dn_0 might be also generated if the duty cycle td1 of the external clock ECLK is large. The unnecessary negative pulse Dn_0 will be propagated earlier and the function of the SMD block 100 will be failed.
(3) Assume that there are some circuit of MCC can solve the issue of FIG. 2, in other words, the signal Dn can have the same clock period as the signal A or Cn, there still have the other issue, for example, there are three delay units in the MCC 106 generating negative pulses Dn−1, Dn and Dn+1 as shown in FIG. 5. These three negative pulses Dn−1, Dn and Dn+1 will propagate until the last stage. However, since every stage of delay units in the BDA 108 will have delay, and this will result in an extension of the negative pulse of the clock E. As shown in FIG. 5, the negative pulse En of the clock E is the combination of the negative pulses Dn and En+1, and as a result, the pulse width pll of the negative pulse En−1 will be larger than the pulse width plh of the clock A. Similar to the first issue, this pulse extension will lead to an error operation in the DDR application.
(4) For example, each delay unit of the FDA 104 includes a NAND2 gate 610 and an inverter 620, while each delay unit of the BDA 108 includes a NAND2 gate 630 and an inverter 640 as shown in FIG. 6A and FIG. 6B. The NAND2 gate 610 of the n-th stage of delay unit outputs a clock Yn1 according to the clock Dn−2 (or VDD) and the clock Cn−1. The NAND2 gate 630 of the n-th stage of delay unit outputs a clock Yn2 according to the clocks Dn and En+1. The inverters 620 and 640 respectively output clocks Cn and En according to the clocks Yn1 and Yn2. The clock Dn−2 (or VDD) and the clock Dn are both at a high level. The clock Cn−1 has a high level while the clock En+1 has a low level as shown in FIG. 6C.
Thus, as shown in FIGS. 6A˜6C, the delay time tdr of the clock Cn relative to the clock Cn−1 is a sum of the gate delay of two serial-connected N-type metal oxide semiconductor (NMOS) transistors M2 and M3 and one P-type metal oxide semiconductor (PMOS) transistor M4, while the delay time tdf of the clock En relative to the clock En+1 is a sum of the gate delay of one PMOS transistor M1 and one NMOS transistor M5. Thus, the delay time tdr will not be equal to the delay time tdf. The difference of one delay unit might not be huge. However, a lot of delay units will accumulate a significant difference between the delay time of the clock Dn relative to the clock B and the delay time of the clock E relative to the clock Dn since the clock period will need a lot of delay units to propagate.
(5) As shown in FIG. 7, the propagating time t-pos of the positive pulse, i.e. the delay time of the clock Cn relative to the clock B, is the same as the propagating time t-neg of the negative pulse, i.e. the delay time of the clock E relative to the clock Dn. However, when the positive pulse of the clock Cn has a non-trivial pulse width, the rising edge of the positive pulse of the clock Cn will occur by a delay time t-miss relative to the falling edge of the negative pulse of the clock E as triggered by the clock A. As a result, the delay time tv of the clock Dn relative to the clock B is (t-pos+t-miss)=Tk−d1−d2, and the total delay time of the internal clock ICLK relative to the external clock ECLK is (d1+(d1+d2)+tv+t-neg+d2)=2(Tk−t-miss). Therefore, the purpose of synchronizing the internal clock ICLK and external clock ECLK cannot be achieved.